Skip to main content

Ctrl+K

Part I, Understanding the GPU

GPU Execution Model
What Makes a Kernel Fast
Data Layout and Its Notation
Tensor Core Operand Layouts Across GPU Generations
Async Data Movement: TMA
Tensor Cores: tcgen05
Special Memory: TMEM
Async Coordination: mbarriers
Advanced: Cluster Launch Control

Part II, TIRx Overview

Introduction to TIRx
TIRx Layout API

Part III, GEMM: Tiled to SOTA

Building a Tiled GEMM
Pipelining GEMM with TMA
Scaling GEMM with Warp Specialization and Clusters

Part IV, Flash Attention 4

Flash Attention 4

Reference

Reference
Troubleshooting
Compiler Internals
- TIRx lowering pipeline
TIRx Language Reference

Compiler Internals

Compiler Internals#

Internals of the TIRx compiler, for contributors.

TIRx lowering pipeline

previous

Troubleshooting

next

TIRx lowering pipeline

By MLC Community

© Copyright 2026, MLC Community.